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THC63LVDM87_rev.1.00_e copyright?2012 thine electronics, inc. 1/12 thine electronics, inc. block diagram 7 THC63LVDM87 low power / small pa ckage / 24bit color lvds transmitter general description the THC63LVDM87 transmitter is designed to support pixel data transmission between host and flat panel display up to 1080p/wuxga resolutions. the THC63LVDM87 converts 28bits of cmos/ttl data into lvds(low voltag e differential signaling) data stream. the transmitter can be programmed for ris- ing edge or falling edge clocks through a dedicated pin. at a transmit clock frequency of 160mhz, 24bits of rgb data and 4bits of timing and control data (hsync, vsync, de, cont1) are transmitted at an effective rate of 1120mbps per lvds channel. features ? low power 1.8v cmos design ? 5mm x 5mm/49pin/0.65mm pitch vfbga package applicable to non-hdi pcb ? wide dot clock range, 8-160mhz suited for tv signal: ntsc(12.27mhz) - 1080p(148.5mhz) pc signal: qvga(8mhz) - wuxga(154mhz) ? supports 1.8v single power supply ? 1.8v/2.5v/3.3v cmos inputs are supported by setting iovcc=1.8v/2.5v/3.3v ? lvds swing is reducible by rs-pin to reduce emi and power consumption ? pll requires no external components ? supports spread spectrum clock generator ? on chip jitter filtering ? power down mode ? input clock triggering edge is selectable by r/f-pin ttl parallel to serial pll ta +/- tb +/- tc +/- td +/- tclk +/- r/f /pdwn ta0-6 tc0-6 td0-6 transmitter (8 to 160mhz) ttl /cmos 7 rs 7 tb0-6 7 inputs clock (lvds) 8-160mhz lvds outputs (56-1120mbit/on each lvds channel) clkin THC63LVDM87
copyright?2012 thine electronics, inc. 2/12 thine electronics, inc. THC63LVDM87_rev.1.00_e pin out
copyright?2012 thine electronics, inc. 3/12 thine electronics, inc. THC63LVDM87_rev.1.00_e pin description pin name pin # type description ta+, ta- b7, b6 lvds out lvds data out. tb+, tb- c7, c6 lvds out tc+, tc- d7, d6 lvds out td+, td- f7, f6 lvds out tclk+, tclk- e7, e6 lvds out lvds clock out. ta0 ~ ta6 a7,a6,a5,a4,a3,a2,a1 in pixel data inputs. tb0 ~ tb6 c2,d2,e2,f2,b1,c1,d1 in tc0 ~ tc6 e1,f1,g1,g2,g3,g4,g5 in td0 ~ td6 b5,b4,b3,b2,f3,f4,f5 in /pdwn g7 in h: normal operation, l: power down (all outputs are hi-z and all circuits are stand- by mode with minimum current(itccs)) rs c5 in lvds swing mode select. r/f e5 in input clock triggering edge select. h: rising edge, l: falling edge clkin g6 in clock input. io vcc d4 power power supp ly pin for io inputs. vcc c4 power power supply pin for digital circuitry. lvds vcc d5 power power supply pin for lvds outputs. pll vcc e4 power power supply pin for pll circuitry. gnd c3,d3,e3 ground ground pins for common. rs lvds swing(vod, see fig4) h 350mv l 200mv
THC63LVDM87_rev.1.00_e copyright?2012 thine electronics, inc. 4/12 thine electronics, inc. absolute maximum ratings recommended oper ating conditions supply voltage (io vcc) -0.3v ~ +4.0v supply voltage (vcc, pll vcc, lvds vcc) -0.3v ~ +2.1v cmos/ttl input voltage -0.3v ~ (io vcc + 0.3v) lvds transmitter output voltage -0.3v ~ (lvds vcc + 0.3v) lvds total output current -50ma ~ 50ma junction temperature (tj) +125 storage temperature range -55 ~ +125 reflow peak temperature / time +260 / 10sec. maximum power dissipation @+25 1.3w parameter min. typ max units supply voltage (iovcc) 1.62 1.8/2.5/3.3 3.6 v supply voltage (pllvcc / lvdsvcc / vcc) 1.62 1.8 1.98 v operating ambient temperature (ta) -40 85 clock frequency input 8 160 mhz lvds output 8 160 mhz c c c c c c
copyright?2012 thine electronics, inc. 5/12 thine electronics, inc. THC63LVDM87_rev.1.00_e electrical characteristics cmos/ttl dc specifications over recommended operating supply and temper ature ranges unless otherwise specified. lvds transmitter dc specifications over recommended operating supply and temper ature ranges unless otherwise specified. symbol parameter conditions min. typ. max. units v ih18 high level input voltage iovcc=1.62~1.98v 0.65 iovcc iovcc+0.3 v v il18 low level input voltage -0.3 0.35 iovcc v v ih25 high level input voltage iovcc=2.3~2.7v 1.7 iovcc+0.3 v v il25 low level input voltage -0.3 0.7 v v ih33 high level input voltage iovcc=3.0~3.6v 2.0 iovcc+0.3 v v il33 low level input voltage -0.3 0.8 v i inc input current vin=gnd~iovcc -10 10 a symbol parameter conditions min. typ. max. units vod differential ou tput voltage rl=100 normal swing rs=h 250 350 450 mv reduced swing rs=l 140 200 300 mv vod change in vod between complementary output states rl=100 35 mv voc common mode voltage 1.125 1.25 1.375 v voc change in voc between complementary output states 35 mv i os output short circuit current v out =gnd, rl=100 100 ma i oz output tri-state current /pdwn=l, v out =gnd~lvdsvcc -20 20 a
copyright?2012 thine electronics, inc. 6/12 thine electronics, inc. THC63LVDM87_rev.1.00_e supply current over recommended operating supply and temper ature ranges unless otherwise specified. (a) all typ. values are at vcc=1.8v, ta=25 . the 16 grayscal e pattern (fig1) inputs test for a typical display pattern. (b) all max. values are at vcc=1.98v, ta=85 . lvds output full toggle pattern (fig2) produces maximum switching frequency for all the lvds outputs. fig1 16 grayscale pattern symbol parameter condition(*) typ. max. units i tccw transmitter supply current rl=100 cl=5pf rs=h normal swing mode f=37mhz 25 33 ma f=71mhz 30 46 ma f=160mhz 44 79 ma rs=l reduced swing mode f=37mhz 19 27 ma f=71mhz 24 40 ma f=160mhz 38 73 ma i tccs transmitter power down supply current /pdwn = l, all inputs = l or h 1 50 a c c tx+ x= a, b, c, d tclk+ fig2 lvds output full toggle pattern
copyright?2012 thine electronics, inc. 7/12 thine electronics, inc. THC63LVDM87_rev.1.00_e switching characteristics over recommended operating supply and temper ature ranges unless otherwise specified. symbol parameter min. typ. max. units t tcp clk in period 6.25 t 125 ns t tch clk in high time 0.35t 0.5t 0.65t ns t tcl clk in low time 0.35t 0.5t 0.65t ns t tcd clk in to tclk+/- delay (fig4) 5t+3.1 5t+8 ns t ts ttl data setup to clk in 0.8 ns t th ttl data hold from clk in 0.8 ns t lvt lvds transition time 0.6 1.5 ns t top1 output data position0 (t=6.25ns~15ns) -0.15 0.0 +0.15 ns t top0 output data position1 (t=6.25ns~15ns) ns t top6 output data position2 (t=6.25ns~15ns) ns t top5 output data position3 (t=6.25ns~15ns) ns t top4 output data position4 (t=6.25ns~15ns) ns t top3 output data position5 (t=6.25ns~15ns) ns t top2 output data position6 (t=6.25ns~15ns) ns t tpll phase lock loop set 10.0 ms t 7 --- 0 . 1 5 ? t 7 --- t 7 --- 0 . 1 5 + 2 t 7 --- 0 . 1 5 ? 2 t 7 --- 2 t 7 --- 0 . 1 5 + 3 t 7 --- 0 . 1 5 ? 3 t 7 --- 3 t 7 --- 0 . 1 5 + 4 t 7 --- 0 . 1 5 ? 4 t 7 --- 4 t 7 --- 0 . 1 5 + 5 t 7 --- 0 . 1 5 ? 5 t 7 --- 5 t 7 --- 0 . 1 5 + 6 t 7 --- 0 . 1 5 ? 6 t 7 --- 6 t 7 --- 0 . 1 5 + ac timing diagrams 5pf 20% 80% 20% 80% t lvt t lvt lvds output v diff 100 v diff =(ta+)-(ta-) ta+ ta- lvds output load fig3. lvds output load and transition time
copyright?2012 thine electronics, inc. 8/12 thine electronics, inc. THC63LVDM87_rev.1.00_e ac timing diagrams ttl inputs t tcp t ts t th t tch t tcl clk in tx0-tx6 t tcd tclk+ tclk- voc iovcc/2 iovcc/2 iovcc/2 iovcc/2 iovcc/2 fig4. clkin period, high/lo w time, setup/hold timing iovcc gnd gnd iovcc vod r/f=h r/f=l
copyright?2012 thine electronics, inc. 9/12 thine electronics, inc. THC63LVDM87_rev.1.00_e ac timing diagrams phase lock loop set time v diff = 0v v diff = 0v tclk+/- t top1 t top0 t top6 t top5 t top4 t top3 t top2 lvds output td6 td5 td4 td3 td2 td1 td0 td+/- tc6 tc5 tc4 tc3 tc2 tc1 tc0 tc+/- tb6 tb5 tb4 tb3 tb2 tb1 tb0 tb+/- ta6 ta5 ta4 ta3 ta2 ta1 ta0 ta+/- (differential) next cycle previous cycle fig5. lvds output data position vih clkin /pdwn tclk+/- t tpll v diff = 0v fig6. pll lock time
copyright?2012 thine electronics, inc. 10/12 thine electronics, inc. THC63LVDM87_rev.1.00_e note 1)cable connection and disconnection don't connect and disconnect the lvds cable, when the power is supplied to the system. 2)gnd connection connect the each gnd of the pcb whic h THC63LVDM87 and lvds-rx on it. it is better for emi reduction to place gnd cable as close to lvds cable as possible. 3)multi drop connection multi drop connection is not recommended. 4)asynchronous use asynchronous use such as foll owing systems are not recommended.
copyright?2012 thine electronics, inc. 11/12 thine electronics, inc. THC63LVDM87_rev.1.00_e package vfbga
copyright?2012 thine electronics, inc. 12/12 thine electronics, inc. THC63LVDM87_rev.1.00_e notices and requests 1. the product specifications descri bed in this material are subjec t to change without prior notice. 2. the circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. we are not responsible for possi ble errors and omissions in this material. please note if errors or omissions should be fo und in this material, we may not be able to correct them immediately. 3. this material contains our copyright, know-how or other proprietary. c opying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. note that if infringement of any third part y's industrial ownership s hould occur by using this product, we will be exempted fro m the responsibility unless it di rectly relates to the production process or functions of the product. 5. this product is presumed to be used for general electric equi pment, not for the applications which require very high reliability (including medical equipment direct ly concerning people's life, aerospace equipment, or nuclear control eq uipment). also, when using this product for the equipment concerned with the control and safety of the transportation means, the traffic signal equipment, or various types of safety equipment, please do it after ap plying appropriate measures to the product. 6. despite our utmost efforts to im prove the quality and re liability of the product, faults will occur with a certain small pr obability, which is inevitable to a semi-conductor product. therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our produc t cause any social or public damage. 7. please note that this product is not designed to be radiation-proof. 8. customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the foreign ex change and foreign trade control law. thine electronics, inc. e-mail: sales@thine.co.jp

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